1. Field of the Invention
The present invention is related to a phase locked loop and, more particularly, a phase locked loop utilizing a digital frequency synthesizer.
2. Description of the Related Art
One of the circuits that has been particularly useful in communications electronics is the Phase Lock Loop (PLL). A PLL circuit is a circuit that is used for the synchronization of signals. Phase lock loops may be used in a wide variety of electronic circuits, in which signals, containing analog and digital information, are decoded. Phase lock loops may be thought of as synchronizing circuits, in which an output frequency is synchronized, or locked, to a reference frequency. PLLs are also used in mobile communication applications related to such purposes as frequency generation, signal modulation, signal demodulation, data decoding and data encoding. Phase lock loops have application not only in frequency synchronization, but also in frequency synthesis, and frequency generation. PLL's may incorporate divider, multiplier, or mixer circuits in order to create lower, higher, or translated frequencies.
As a consequence, the phase locked loop (PLL) forms the basis of most modern carrier generation synthesizer solutions. The synthesizer technique aims to get a high quality (low phase noise), high frequency oscillator to be locked to a stable, low level, low cost (often crystal derived) source. The frequency synthesizer is commonly used in radio frequency devices to provide generation of local oscillator (LO) high frequency signals. Applications include, for example, the read channel in a hard disk drive, and for RF wireless communications such as cellular and digital cordless telephone local oscillator applications. Several of these applications require low phase noise and small frequency steps of the frequency synthesizer.
For an RF wireless application, a transmitter and receiver require a synthesizer to up convert and down convert modulated and received signals. In some RF wireless examples, a clock frequency of 1100-1200 MHz in small 200 KHz steps is required of the synthesizer to meet the channel spacing requirements. Here again, low phase noise may be required to have a high sensitivity in the receiver and not allow noise power to spill over into adjacent channels. In addition, the need is especially great in the RF wireless and other hand held portable device applications to integrate the entire synthesizer and Voltage Controlled Oscillator (VCO) on a single semiconductor chip, for size, power, manufacturing, and economic reasons.
Thus, two important factors affecting the design of a carrier frequency source are frequency stability and phase noise. Frequency stability generally refers to the stability of the oscillator with respect to temperature and aging, and determines the channel spacing required to contain the modulated carrier signal. Conversely, for a given regulated channel spacing, the frequency stability determines the maximum data rate that can be supported without violating the channel boundary. Phase noise generally refers to the oscillator phase jitter resulting in a broadband component to the carrier signal which will extend into adjacent channels. If the phase noise is too high, this can corrupt the modulation source itself, and limit adjacent channel selectivity due to reciprocal mixing.
Previous frequency synthesizers use single loops or complex multi-loop solutions to generate the desired output frequency and step size for a local oscillator. In the production of this high frequency, conventional synthesizers use a high multiplication of the original input reference signal. But as a byproduct, they also detrimentally multiply the frequency step size, the phase noise, and generate spurious signals. This multiplication in the conventional synthesizer (both for its advantages and disadvantages) is done by the dividers in the PLL loops, and by the mixer in the final loop.
A more recent extension of the basic PLL based synthesizer is the fractional-N device. A simple form of PLL synthesizer contains a voltage controlled oscillator (VCO) operating at the required carrier frequency, a frequency divider, which is a digital divider circuit, a phase detector circuit and a loop filter. FIG. 1 illustrates this type of simple conventional synthesizer. The synthesizer circuit 9 acts to lock its output to the reference frequency (DIN), resulting in an output frequency (carrier) of VCO_OUT. The input reference frequency DIN is compared in a phase/frequency detector 2 to that of the divided down feedback from the output of a divider 5 (VCO_OUT/N), as a result of the frequency produced by a VCO 6. The output of the phase/frequency detector 2 is filtered by a loop filter 8, which produces a voltage to control the frequency output (VCO OUT) of VCO 6.
A fractional divide-by-N PLL (fractional-N) is used to get small frequency steps, and a narrow bandwidth is used to filter out the spurious signals generated by the method. However, the fractional divide-by-N also puts spurious signals inside the loop bandwidth and sigma delta techniques are used in an attempt to eliminate the effects of the fractional spurs. Further, the phase noise requirement for wireless applications, for example, is so low that an external VCO is required in a fractional-N synthesizer. As can be seen, a fractional divide-by-N synthesizer can produce small frequency steps, but usually requires an external VCO for phase noise and a narrow bandwidth filter for spurious signals generated inside the loop bandwidth to eliminate the effects of the fractional spurs. Consequently, the fractional-N technique has limited improvement usefulness.
One conventional multi-loop solution uses a fractional-N PLL coupled as the input reference signal to a translational PLL to provide filtering through the translation loop. The divider and translation loop arrangement produces relatively high frequency output components which are filtered and produce low noise side bands due to the low multiplication factors used. The mixer in the final translation PLL produces a low phase noise output signal that has been filtered by the translation loop filters and which may be fully integrated on a semiconductor chip. While the translational PLL technique improves the loop bandwidth, a second PLL is necessary to generate the mixer local oscillator (LO) signal. This additional PLL increases the circuit complexity, power consumption and cost.
Recently, direct digital synthesizers (DDS) based on time domain interpolation have emerged as an attractive option for frequency generation, particularly for wide bandwidth applications. For portable communication applications, implementations that have a low power consumption specification are particularly valuable. In one known approach, a reference clock signal is used to derive another frequency signal based on a relationship between both signals. An accumulator operating in response to the reference clock signal accumulates a digital value related to the relationship between the desired frequency signal and the reference clock signal until a maximum value is reached and an accumulator overflow occurs. The accumulator overflow is used to trigger the output of the desired frequency signal and the operation of any correction circuitry for perfecting the signal.
Quantized Interpolated Edge Timed (QuIET) synthesis is one such DDS technique that uses a reference PLL synthesizer to generate the input clock. In wireless applications, the transceiver LO frequencies are generated at the output of the QuIET synthesizer. In applications where intra-stage filtering between the RF modulator and the power amplifier are not used, the QuIET DDS must meet the phase noise and spurious requirements in the receive frequency bands and in the transmit adjacent bands. This additional PLL increases the circuit complexity, power consumption and cost. Some of the problems with the QuIET synthesizer implementation are the DLL delay quantization and mismatch can cause spurs, which are tethered into the phase noise. Also the noise in-band is often too high, so sigma-delta modulators noise shaping is applied, further increasing implementation area and cost. Again, while the QuIET synthesis technique improves loop bandwidth, an additional PLL is necessary to generate the mixer local oscillator (LO) signal.
Accordingly, there is a need for a synthesizer circuit that does not suffer from the problems seen in the prior art with translational PLLs and direct digital sythesizers. There is a need for a synthesizer circuit with a large bandwidth for generating a high frequency in small frequency steps with low phase noise, in a small, low cost, low power solution, which is fully integrated on a semiconductor chip. It would be desirable for such a solution to not require an additional reference PLL to generate the input signal.